Counters Implemented in Single Electron Technology

Single Electron Tunneling (SET) is an emerging technology which offers greater scaling potential than MOS. The SET technology offers the ability to control the transport of individual electrons. In this paper we investigate the implementation of 7=3 and 7j2 counters in SET technology. Counters are elementary building blocks which can be utilized for the design of larger arithmetic structures, such as multipliers. Given that in Boolean gate design style counters are commonly implemented using full adders, we first present SET implementations of full adders in Boolean gate and threshold gate design style. Second, we compare three design alternatives for 7=3 and 7j2 counters, namely Boolean gate full adder, threshold gate full adder, and pure threshold gate respectively. The best candidate for a 7=3 counter implementation is the pure threshold gate based design, which requires three threshold gates that can be implemented in SET using 15 tunnel junctions and 45 capacitors. Third, we verify the 7=3 counters implemented in threshold gate full adder and pure threshold gate by means of simulation, and present the simulation results obtained. Keywords—single electron, SET, threshold logic, Boolean logic, parallel counters